Publication details
Binary decision diagrams on modern hardware
| Authors | |
|---|---|
| Year of publication | 2023 |
| Type | Article in Proceedings |
| Conference | Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design – FMCAD 2023 |
| MU Faculty or unit | |
| Citation | |
| Web | https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_20 |
| Doi | http://dx.doi.org/10.34727/2023/isbn.978-3-85448-060-0_20 |
| Keywords | Binary Decision Diagram; Automated Reasoning; Hashing |
| Attached files | |
| Description | Binary decision diagrams (BDDs) are one of the fundamental data structures in formal methods and computer science in general. However, the performance of BDD-based algorithms greatly depends on memory latency due to the reliance on large hash tables and thus, by extension, on the speed of random memory access. This hinders the full utilisation of resources available on modern CPUs, since the absolute memory latency has not improved significantly for at least a decade. In this paper, we explore several implementation techniques that improve the performance of BDD manipulation either through enhanced memory locality or by partially eliminating random memory access. On a benchmark suite of 600+ BDDs derived from real-world applications, we demonstrate runtime that is comparable or better than parallelising the same operations on eight CPU cores. |