Project information
Techniques for automatic verification and validation of software nad hardware systems
- Project Identification
- 1ET408050503
- Project Period
- 1/2005 - 12/2009
- Investor / Pogramme / Project type
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Academy of Sciences of the Czech Republic
- Information society (National programme of research)
- MU Faculty or unit
- Faculty of Informatics
- Keywords
- Computer aided and automatic verication, theory and technology of modellingof large systems, methodology of software engineering, embedded systems, parallel and distributed systems, real time systems.
The main objective of the project is to create a theoretical and methodological base for computer-aided and automatic verification and validation of large software and hardware systems. The project aims to support the development of methodologies, technologies and tools of software engineering in automatic and computer-aided verification. The project is to contribute to the research into new technologies for a realistic modelling of large systems, including real-time systems and probabilistic systems, especially with respect to their safety. The aim is to design effective implementations of these models as well as efficient verification technologies based on such models. The project will focus on embedded, distributed and parallel systems. Taking into consideration the complexity of verification processes, the aim is to design methodologies that will make the maximum possible use of new information technologies, such as parallel and distributed computing and hierarchical memories.
Results
Publications
Total number of publications: 94
2007
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On Decidability of LTL+Past Model Checking for Process Rewrite Systems
Year: 2007, type: Appeared in Conference without Proceedings
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Parallel Algorithms for Finding SCCs in Implicitly Given Graphs
Formal Methods: Applications and Technology, year: 2007
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Parallel Model Checking and the FMICS-jETI Platform
Proceedings Twelfth IEEE International Conference on Engineering of Complex Computer Systems, year: 2007
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ProbDiVinE
Year: 2007
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ProbDiVinE: A Parallel Qualitative LTL Model Checker
Fourth International Conference on the Quantitative Evaluation of Systems (QEST'07), year: 2007
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Relaxed Cycle Condition Improves Partial Order Reduction
3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS 2007), year: 2007
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Scalable Multi-core LTL Model-Checking
Model Checking Software, year: 2007
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Verifying VHDL Designs with Multiple Clocks in SMV
Formal Methods Applications and Technology, 11th International Workshop on Formal Methods for Industrial Critical Systems, FMICS 2006, and 5th International Workshop on Parallel and Distributed Methods in Verification, PDMC 2006, year: 2007
2006
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11th International Workshop on Formal Methods for Industrial Critical Systems
Year: 2006, type: Workshop
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Architectural Interoperability Checking in Visual Coordination Networks
Combined Proceedings of the Second International Workshop on Coordination and Organization (CoOrg 2006) and the Second International Workshop on Methods and Tools for Coordinating Concurrent, Distributed and Mobile Systems (MTCoord 2006), year: 2006