Publication details
Parallelization of brute-force attack on MD5 hash algorithm on FPGA
| Authors | |
|---|---|
| Year of publication | 2019 |
| Type | Article in Proceedings |
| Conference | 32nd International Conference on VLSI Design, VLSID 2019 |
| MU Faculty or unit | |
| Citation | |
| web | http://dx.doi.org/10.1109/VLSID.2019.00034 |
| Doi | http://dx.doi.org/10.1109/VLSID.2019.00034 |
| Keywords | LUT; HDL; GPU; IP core |
| Attached files | |
| Description | FPGA implementation of MD5 hash algorithm is faster than its software counterpart, but a pre-image brute-force attack on MD5 hash still needs 2 power 128 iterations theoretically. This work attempts to improve the speed of the brute-force attack on the MD5 algorithm using hardware implementation. A full 64-stage pipelining is done for MD5 hash generation and three architectures are presented for guess password generation. A 32/34/26-instance parallelization of MD5 hash generator and password generator pair is done to search for a password that was hashed using the MD5 algorithm. The total performance of about 6G trials/second has been achieved using a single Virtex-7 FPGA device. |