Publication details
Routing and Level 2 Addressing in a Hardware Accelerator for Network Applications
| Authors | |
|---|---|
| Year of publication | 2006 |
| Type | Article in Proceedings |
| Conference | ICT 2006, 13th International Conference on Telecommunications |
| MU Faculty or unit | |
| Citation | |
| Field | Use of computers, robotics and its application |
| Keywords | routing; L2 addressing; hardware acceleration |
| Description | Personal computers are known to be highly usable as internet routers. To overcome their throughput limitations, a hardware accelerator can be employed. For the purposes of packet classification in the accelerator, we investigate a way to combine routing, level 2 addressing, and packet filtering into a single lookup structure. This paper describes the first part of the process: a method to combine routing and level 2 addressing to a single lookup. A formal model of routing and level 2 addressing is presented and used to prove correctness of the method and its equivalence to operating system behaviour. |
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