Project information
Automated software verification
- Project Identification
- GA201/06/1338
- Project Period
- 1/2006 - 12/2008
- Investor / Pogramme / Project type
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Czech Science Foundation
- Standard Projects
- MU Faculty or unit
- Faculty of Informatics
- Keywords
- verification, model-checking, software, components
The main objective of the project is to create a theoretical and methodological base for computer-aided and autotic verification and validation of software systems. The project aims to support the development of methodologies, technologies and tools of software engineering in automatic and computer-aided verification. The project is to contribute to the research into new technologies for a realistic modelling of software systems, including real-time systems, especially with respect to their safety. The aim is to design effective implementations of these models as well as efficient verification technologies based on such models. The project will focus on embedded distributed and parallel systems. Taking into consideration the complexity of verification processes the aim is to design methodologies that will make the maximum possible use of new information technologies, such as parallel and distributed computing and hierarchical memories.
Results
The main objective of the project is to create a theoretical and methodological base for computer-aided and autotic verification and validation of software systems.
Publications
Total number of publications: 45
2007
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DiVinE Multi-Core
Year: 2007
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I/O Efficient Accepting Cycle Detection
19th International Conference on Computer Aided Verification, year: 2007
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Model Checking Large Finite-State Systems and Beyond
33rd Conference on Current Trends in Theory and Practice of Computer Science, year: 2007
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Parallel Algorithms for Finding SCCs in Implicitly Given Graphs
Formal Methods: Applications and Technology, year: 2007
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Parallel Model Checking and the FMICS-jETI Platform
Proceedings Twelfth IEEE International Conference on Engineering of Complex Computer Systems, year: 2007
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ProbDiVinE
Year: 2007
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Relaxed Cycle Condition Improves Partial Order Reduction
3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS 2007), year: 2007
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Scalable Multi-core LTL Model-Checking
Model Checking Software, year: 2007
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Tutorial: Parallel Model Checking
Model Checking Software, year: 2007
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Verifying VHDL Designs with Multiple Clocks in SMV
Formal Methods Applications and Technology, 11th International Workshop on Formal Methods for Industrial Critical Systems, FMICS 2006, and 5th International Workshop on Parallel and Distributed Methods in Verification, PDMC 2006, year: 2007