Publication details
In-silico generation of random bit streams
| Authors | |
|---|---|
| Year of publication | 2020 |
| Type | Article in Periodical |
| Magazine / Source | Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment |
| MU Faculty or unit | |
| Citation | |
| Web | https://doi.org/10.1016/j.nima.2020.164480 |
| Doi | http://dx.doi.org/10.1016/j.nima.2020.164480 |
| Keywords | Random number generation; Silicon Photomultipliers; Cryptography |
| Description | Silicon PhotoMultipliers (SiPM) are rapidly approaching a significant maturity stage, making them a well recognised platform for the development of evolutionary and novel solutions in a wide range of applications for research and industry. However, they are still affected by stochastic terms, notably a high Dark Count Rate (DCR), limiting their use when single photo-electron pulses convey the required information, for instance in chemiluminescence or fluorescence analysis of biological samples. In such applications, randomness of the spontaneous generation of carriers triggering the avalanche and the rate of occurrences is significantly decreasing the sensitivity of the system against solutions based, for instance, on traditional photo-multiplier tubes. However, unpredictability of the "dark" pulses has a potential value in domains connected to encryption and, in general terms, cybersecurity. "Random Power' is a project approved within the ATTRACT call for proposals (https://attract-eu.com), having as a main goal the generation of random bit streams by properly analysing the time sequence of the Dark Pulses. The principle has been proven using laboratory equipment and its value assessed applying the National Institute of Standard and Technology (NIST) protocols, complemented by other test suites. The advantages against competing techniques have been thoroughly analysed and the development of a dedicated board, integrating the system in a low cost, low power, scalable design is on-going. The principle, protected by a patent application entered its international phase by the time of writing (application no.102018000009064, deposited at the Office of the Minister of Economic Development, as required by the Italian law; international PCT extension no.PCT/IB2019/058340 deposited in October 2019) will be described, together with the results obtained so far, the current development stage including an FPGA embedded Time-To-Digital Converter (TDC) and future perspectives. |