doc. RNDr. Vojtěch Řehák, Ph.D.
Vice-dean for curricula and internationalisation, Faculty of Informatics
Office: A408
Botanická 554/68a
602 00 Brno
Phone: | +420 549 49 4687 |
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E‑mail: |
social and academic networks: |
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Total number of publications: 68
2006
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Formal Verification of a FIFO Component in Design of Network Monitoring Hardware
10 years of CESNET - CESNET CONFERENCE 2006, year: 2006
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Formal Verification of the CRC Algorithm Properties
Proceedings of 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS 2006), year: 2006
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On Decidability of LTL Model Checking for Process Rewrite Systems
FSTTCS 2006: 26th International Conference on Foundations of Software Technology and Theoretical Computer Science, 26th International Conference, Kolkata, India, December 13-15, 2006, Proceedings, year: 2006
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On Decidability of LTL Model Checking for Weakly Extended Process Rewrite Systems
Year: 2006, type: R&D Presentation
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Packet Filtering for FPGA-Based Routing Accelerator
CESNET Conference 2006 Proceedings, year: 2006
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Refining Undecidability Border of Weak Bisimilarity.
Proceedings of the 7th International Workshop on Verification of Infinite-State Systems (INFINITY'05), year: 2006
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Routing and Level 2 Addressing in a Hardware Accelerator for Network Applications
ICT 2006, 13th International Conference on Telecommunications, year: 2006
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Routing, L2 Addressing, and Packet Filtering in a Hardware Engine
Proceedings of MEMICS 2006, year: 2006
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Weakly Extended Process Rewrite Systems
Year: 2006, type: Appeared in Conference without Proceedings
2005
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CRC64 Algorithm Analysis and Verification
Year: 2005, type: R&D Presentation